Consolidate bugs of PCIe examples

Hi,

I'm playing around with PCIe on Arria II.

As you know, in order to use PCIe, you need a lot of "supporting" logics, such as computing the available credit, arbitration between multiple DMA/Tx/Completor ... etc .. However, Altera doesn't have a "formal" release for these ware and I've been digging on the Example provided whenever the PCIe core is instantiate.

So, my guess is that this "reference design" is not BUG-FREE. Hopefully, the mass community can update bugs so that this core is stable enough.

So far, I found 1 bug:

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- in the file altpcierd_rxtx_downstream_intf.v:

- the logic that controls the mem_wr_ena signal,

if(rx_start_write==1'b1) begin ....

else if(rx_dv==1'b1)

mem_wr_ena <= 1'b1;

mem_wr_addr <= mem_wr_addr+1;

else

...

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The error happens when you poll one of the registers while DMA is running.

it condition should be (rx_dv = 1'b1 && cstate_rx= RX_DV_PAYLD)

...

without condition of cstate_rx, the register is accidentally written by rx_dv which is asserted during some other transactions,

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