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Altera_Forum's avatar
Altera_Forum
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15 years ago

clock recovery

Hi everyone:

I have a question:

I have a cycloneII FPGA to receive the bitstream externally by LVDS interface. There are now two links, one is for data (160Mbps), one is for clock(80Mhz). The clock edge is already aligned to the middle of the data valid period by the trasnsmitter(another FPGA). So in the receiver FPGA, a ddr_in is used to half the speed of data and a pll is used to lock the clock, in this way, sample can be done at every rising clock edge.

My question is that is there any methods to remove the clock link, just using the data link and recover the lock from that? (the data stream has been 8b10b encoded)

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I'm afraid it's not possible to perform clock recovery in your case.

    Clock recovery is only possible with GX blocks, which are not available in Cyclone II and don't work at suck low rates.

    However, at such rates, you might get away with using just a local clock to receive the data. Check Xilinx's XAPP225 for an example.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    A GXB receiver has a dedicated analog PLL for clock recovery. But it doesn't work below about 600 MBPS data rate. As recently suggested in the forum, the DPA circuitry of Stratix and Arria FPGAs can be used for clock recovery with some complementary logic. Finally the PLL dynamic phase shift offered by Cyclone III and other newer chips opens an option of software clock recovery with a limited lock range of e.g. +/- 1000 ppm deviation between transmitter and receiver reference clock. I've used it in an experimental setup up to 240 MBPS over ethernet magnetics and CAT5 cable.

    The basic idea is to sense the position of the data edge and adjust the PLL phase to keep it almost centered between the sampling clock edges.