clock recovery

A GXB receiver has a dedicated analog PLL for clock recovery. But it doesn't work below about 600 MBPS data rate. As recently suggested in the forum, the DPA circuitry of Stratix and Arria FPGAs can be used for clock recovery with some complementary logic. Finally the PLL dynamic phase shift offered by Cyclone III and other newer chips opens an option of software clock recovery with a limited lock range of e.g. +/- 1000 ppm deviation between transmitter and receiver reference clock. I've used it in an experimental setup up to 240 MBPS over ethernet magnetics and CAT5 cable.