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Altera_Forum's avatar
Altera_Forum
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15 years ago

clock recovery

Hi everyone: I have a question: I have a cycloneII FPGA to receive the bitstream externally by LVDS interface. There are now two links, one is for data (160Mbps), one is for clock(80Mhz). Th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm afraid it's not possible to perform clock recovery in your case.

Clock recovery is only possible with GX blocks, which are not available in Cyclone II and don't work at suck low rates.

However, at such rates, you might get away with using just a local clock to receive the data. Check Xilinx's XAPP225 for an example.