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Altera_Forum's avatar
Altera_Forum
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18 years ago

Clock enable bug with FIR compiler v3.3.1 and v6.1

I have found a clock enable bug with FIRs generated with FIR compiler v3.3.1 and v6.1. The bug is not present in FIR compiler v3.3.0 when fixed coefficients are used. With clken always high the FIR generates the correct output, however if input samples are repeated for two clocks, and a clock enable is used to reduce the effective clock rate by a factor of 2, a strange response results. Note however that the impulse response is still correct.

clken always 1

time domain response to LFM input obtained via ModelSim/Matlab:

http://home.pacific.net.au/~nlbrine/ClkEn1_plot.jpg

impulse response obtained via ModelSim:

http://home.pacific.net.au/~nlbrine/ClkEn1_impulse.jpg

clken 1,0,1,0,... input samples repeated for two clocks each

time domain response to LFM input obtained via ModelSim/Matlab:

http://home.pacific.net.au/~nlbrine/ClkEn2_plot.jpg

impulse response obtained via ModelSim:

http://home.pacific.net.au/~nlbrine/ClkEn2_impulse.jpg

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I did not have too many problems with FIR 6.1. However, having said that, I haven't played much with the enable signal.

    While I was browsing through the user guide, I did came across the following statement: " Avalon-ST registers are NOT connected to this clock enable signal."

    Unfortunately, starting from version 6.1, the FIR core is now mainly controlled by Avalon-ST interfaces. Therefore, it would seem like you probably need to build extra logics to control these Avalon-ST registers. Without these extra control logics, I imagine you would see some anomalies (and I suspect this is also the source of your problem...) Hope that helps...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I suggest that DO NOT play much with the enable signal and don't use as a control signal for reducing the clock rate.