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Altera_Forum
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19 years ago

Clock enable bug with FIR compiler v3.3.1 and v6.1

I have found a clock enable bug with FIRs generated with FIR compiler v3.3.1 and v6.1. The bug is not present in FIR compiler v3.3.0 when fixed coefficients are used. With clken always high the FIR...
Altera_Forum's avatar
Altera_Forum
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19 years ago

I suggest that DO NOT play much with the enable signal and don't use as a control signal for reducing the clock rate.