Clock enable bug with FIR compiler v3.3.1 and v6.1

I did not have too many problems with FIR 6.1. However, having said that, I haven't played much with the enable signal.

While I was browsing through the user guide, I did came across the following statement: " Avalon-ST registers are NOT connected to this clock enable signal."

Unfortunately, starting from version 6.1, the FIR core is now mainly controlled by Avalon-ST interfaces. Therefore, it would seem like you probably need to build extra logics to control these Avalon-ST registers. Without these extra control logics, I imagine you would see some anomalies (and I suspect this is also the source of your problem...) Hope that helps...