Clarity to a statement within the PFL Intel FPGA IP User Guide wrt pulsing pfl_nreconfigure pin low

Clarity is required 2 statements within the 'Parallel Flash Loader Intel FPGA IP User Guide' wrt pulsing pin low to initiate a new reconfiguration :

Page 20 states :

1.3.6.1 .... 3. After 15 clock cycles, pulse the pfl_nreconfigure input pin to low

Page 21 states :

1.3.6.2 Bullet point 2 last sentence :

The pfl_nreconfigure signal pulsed low for greater than one pfl_clk_cycle

So from the above 2 statements to initiate reconfiguration do we need to :

After pfl_nreset goes '1' (out of reset) :

Pulse the pfl_nreconfigure input pin to low after 15 clock cycles and keep it low for greater than 1 pfl_clk_cycles

Please confirm ...