Forum Discussion
Knug
Contributor
ContributorClarity to a statement within the PFL Intel FPGA IP User Guide wrt pulsing pfl_nreconfigure pin low
Clarity is required 2 statements within the 'Parallel Flash Loader Intel FPGA IP User Guide' wrt pulsing pin low to initiate a new reconfiguration :
Page 20 states :
1.3.6.1 .... 3. After 1...
Ash_R_Altera
Regular Contributor
Regular ContributorYes, the minimum pulse width for the pfl_nreconfigure = '0' should be one pfl_clk cycle.
