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Knug's avatar
Knug
Icon for Contributor rankContributor
5 years ago

Clarity to a statement within the PFL Intel FPGA IP User Guide wrt pulsing pfl_nreconfigure pin low

Clarity is required 2 statements within the 'Parallel Flash Loader Intel FPGA IP User Guide' wrt pulsing pin low to initiate a new reconfiguration : Page 20 states : 1.3.6.1 .... 3. After 1...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Kevin,


Your understanding is correct.

Once the pfl_nreset pin is 'high' ('1'), wait for 15 pfl_clk cycles and then drive pfl_nreconfigure to 'low' ('0').


Regards.


  • Knug's avatar
    Knug
    Icon for Contributor rankContributor
    5 years ago

    BUT pulse pfl_nreconfigure signal low after 15 pfl_clk cycles for greater than 1 pfl_clk_cycle.

    Please reconfirm ..