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VMots's avatar
VMots
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4 years ago

cascading pll with emif core (stratix10)

Hello!

I have several emif (ddr4) controllers which everyone have it's own reference clock (from package pin) but I want to feed it from pll when I connect it together and try to implement it I get next error messege (only one is shown):

Error(20181): The permit_cal input port of IOPLL "emif_ed_x7_inst|emif_x32_3|emif_x32_s10_2|arch|arch_inst|pll_inst|pll_inst" is not connected correctly. Enable and export the permit_cal port of downstream IOPLL "emif_ed_x7_inst|emif_x32_3|emif_x32_s10_2|arch|arch_inst|pll_inst|pll_inst" with the Platform Designer GUI and connect to the locked output of upstream IOPLL "u0|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll"

but I do not find where to enable this port in the emif ip...

Can someone help me with this? Or may be advise another solution?

Best regards

13 Replies

  • VMots's avatar
    VMots
    Icon for New Contributor rankNew Contributor
    4 years ago

    One more addition: I use Quartus Prime pro 21.2.0

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Are you trying to use the core clocks sharing option in the EMIF IP?

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi VMots,

    I'm Adzim. Thank you for using the Intel Community.

    I've found a KDB for this error message. Link here.

    You might need to follow the resolution in there.

    I think you can enable it in the IOPLL IP under the Cascading tab.

    I share the screenshot for that.

    Please let me know if that helpful.

    Thanks,

    Adzim

    • VMots's avatar
      VMots
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      4 years ago

      I am already see this solution but this is not iopll core but the emif core and it need to have permit_cal input.

    • VMots's avatar
      VMots
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      4 years ago

      That wasn't a question, how to connect two pll's.

      If you have 7 ddr memory controllers in one FPGA it require 14 pins for clock - it is too expensive while one is enough but looks like the intel not give us such possibility.

      While you feed ddr memory controllers from plls quartus give you error that you need to connect feedin pll pin with name pll_lock with ddr memory controller pll pin called permit_cal

      But permit_cal input is unaccessible from ip configurator

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi VMots,


    Do you can share the design with me so that I can replicate the error and debug it?


    Thanks,

    Adzim