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VMots
New Contributor
New Contributorcascading pll with emif core (stratix10)
Hello!
I have several emif (ddr4) controllers which everyone have it's own reference clock (from package pin) but I want to feed it from pll when I connect it together and try to implement it I get...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Viktor,
Thanks for sharing the file.
I can see it's the synthesize error.
The Stratix 10 EMIF IP doesn't support PLL cascading as mention in the EMIF User Guide below.
I think you have to reconfigure the PLL reference clock that connect to the EMIF IPs.
Regards,
Adzim
