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VMots's avatar
VMots
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4 years ago

cascading pll with emif core (stratix10)

Hello! I have several emif (ddr4) controllers which everyone have it's own reference clock (from package pin) but I want to feed it from pll when I connect it together and try to implement it I get...
AdzimZM_Altera's avatar
AdzimZM_Altera
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4 years ago

Hi VMots,


Do you can share the design with me so that I can replicate the error and debug it?


Thanks,

Adzim


VMots's avatar
VMots
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4 years ago

Hello Adzim!

I can share project archive but it too big to share it here .

Thank you

Viktor