New Contributor
Super ContributorThat's for cascading PLLs into each other, not from a PLL to an IP:
Simply turn off the cascading option in the PLL parameters and connect the PLL output to the EMIF clock input. There is no option for a permit_cal input into the EMIF IP because it's not needed.
New ContributorThat wasn't a question, how to connect two pll's.
If you have 7 ddr memory controllers in one FPGA it require 14 pins for clock - it is too expensive while one is enough but looks like the intel not give us such possibility.
While you feed ddr memory controllers from plls quartus give you error that you need to connect feedin pll pin with name pll_lock with ddr memory controller pll pin called permit_cal
But permit_cal input is unaccessible from ip configurator
Super ContributorNo, this is where you use the EMIF core clock sharing option I was asking about originally. You feed the clock to one EMIF and then that EMIF sends the clock to others. Again, there is no permit_cal pin because it's not part of the IP. The option you mention is for cascading PLLs (and just PLLs). From the EMIF parameterization training (https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1122.html):
New Contributoryou speaking about core clock network sharing this is not that I need...
I need pll reference clock feeding (pll is inside emif core)
