New ContributorHello! I'm trying to implement DDR4 40bit-wide interface with 3 devices MT40A512M16LY-062E. When I connect only one of 3 devices to the project, calibration and data exchange do well, but when I connect all 3 devices - calibration fails. Why it happens and how can it be fixed?
Regular ContributorHi Andrey_Fazan,
I hope you're doing well.
Do you still get the error when enable all memories on the board?
Regards,
Adzim
New ContributorHi, Adzim,
I still have some problems with all memories, but it went better. What did I do:
- in dqs pins from 39 to 0 I set memory groups in this order: lower and upper A (device 3), upper and lower B (device 2), and lower C. (device 1) (why did I set upper and then lower A - in other case, I have only 3/5 dqs group calibrated)
- in IP parameters: MemIO tab -> memory IO settings subtab -> Output drive strength setting - 40 ohm and ODT Rtt nominal value - 48 Ohm
Now, I have these calibration results:
+---------------------------------------+
; Calibration Status Per Group ;
+-------+--------+----------------------+
; Group ; Status ; Error Stage ;
+-------+--------+----------------------+
; 0 ; Pass ; N/A ;
; 1 ; Pass ; N/A ;
; 2 ; Pass ; N/A ;
; 3 ; Pass ; N/A ;
; 4 ; Fail ; Write Per-bit Deskew ;
+-------+--------+----------------------+
So, now I can work with 32bit memory without ECC, but it still not what I expected. Moreover, we are going to make board for other project with at least 64bit wide memory interface, so I still need to solve this problem. I attach report and configuration for current project
Regular ContributorHi Andrey,
Have you changed the device or board?
Because I notify that you used difference speedgrade in you EMIF IP.
I'm not understand on how do you configured the memory order.
Can you show the board design topology for the memory device connection?
Maybe you can draw a diagram for all groups.
For your new project, I think you should run the board simulation first to identify the optimum OCT value that your board can get.
Regards,
Adzim
New ContributorHi, Adzim,
I can share the PCB document for Altium Designer, it could be more informative.
Short info:
- FPGA is A9.DD1;
- sdram bank C is A12.D3 (first device along the CK track, as I mentioned before);
- bank B - A12.D2,
- bank A - A12.D1;
At the moment banks are connected to emif in this order (it gives the best calibration results, 4/5):
dq pins of emif: [39===sdram_a[7...0], sdram_a[15...8], sdram_b[15...8], sdram_b[7...0], sdram_c===0].
So, the last dqs group (sdram_a[7...0], or dq_pin[39...32]) could not be calibrated with all devices together. When I swap sdram_a[7...0] and sdram_a[15...8], I have only 3/5 (I attach reports for each variation of order, see the first line to define it).
Thanks!
Regular ContributorHi Andrey,
Thanks for sharing those files.
It's seems like the sdram_a[7...0] is the only group that failed in the calibration
Even after you swapping the group with sdram_a[15...8].
The sdram_a[15...8] group can do the calibration but not for the sdram_a[7...0].
There is one thing that I notice in the calibration report which is the VREFIN setting for the sdram_a[7...0] group is slightly lower than other.
Maybe you can take a look on the voltage for this group when running the calibration.
Also make sure that there is no connectivity problem on board.
You can try to set the Memory I/O Settings as below.
• Output drive strength setting = RZQ/7 (34 ohm)
• Dynamic ODT (Rtt_ WR) value = Dynamic ODT off.
• ODT Rtt nominal value = ODT Disable.
• Rtt Park = RZQ /3 (80 Ohm)
Thanks,
Adzim
New ContributorHi, Adzim
These settings didn't help
You can try to set the Memory I/O Settings as below.
• Output drive strength setting = RZQ/7 (34 ohm)
• Dynamic ODT (Rtt_ WR) value = Dynamic ODT off.
• ODT Rtt nominal value = ODT Disable.
• Rtt Park = RZQ /3 (80 Ohm)
Regular ContributorHi Andrey,
Can you create a 32-bit data configuration and used the sdram_a[7...0] as the last group?
Thanks
New ContributorHi, Adzim
I created such interface. Both sdram_a[7...0] and sdram_a[15...8] can be calibrated with sdram_b and sdram_c. I also tried to create an interface with only sdram_a and sdram_b (without sdram_c). Calibration was not successful. I attach report for each situation (as always the order of connection is at the top of each document)
Regular ContributorHi Andrey,
Thank you for sharing those files.
It's looks like the sdram_a cannot be worked when enabling 16bit and combing with other memory.
I'm not sure what is the reason for that but I think it's could be related with the voltage.
So can you probe on your board at the sdram_a[7...0] and sdram[15...8] to analyze the voltage?
Regards,
Adzim
ContributorHi
just to make sure , do you use the 240 resistor as RZQ resistor on your board ?
Regular ContributorHi Andrey,
Do you have any update on this?
Regards,
Adzim
New ContributorHi, Adzim
Is it possible to get PCB layout of arria 10 soc development kit? It could help us check if our layout of DDR4 devices is correct.
Thank you!
ContributorHi
You can download the PCB layout of arria 10 soc development kit from the link here
New ContributorHi!
just to make sure , do you use the 240 resistor as RZQ resistor on your board ? - Yes, we use it
So can you probe on your board at the sdram_a[7...0] and sdram[15...8] to analyze the voltage? - Everything with voltage is fine, but we need to update our board, so I will tell later about results
Thank you!
