New Contributor
Regular ContributorHi Andrey,
Have you changed the device or board?
Because I notify that you used difference speedgrade in you EMIF IP.
I'm not understand on how do you configured the memory order.
Can you show the board design topology for the memory device connection?
Maybe you can draw a diagram for all groups.
For your new project, I think you should run the board simulation first to identify the optimum OCT value that your board can get.
Regards,
Adzim
New ContributorHi, Adzim,
I can share the PCB document for Altium Designer, it could be more informative.
Short info:
- FPGA is A9.DD1;
- sdram bank C is A12.D3 (first device along the CK track, as I mentioned before);
- bank B - A12.D2,
- bank A - A12.D1;
At the moment banks are connected to emif in this order (it gives the best calibration results, 4/5):
dq pins of emif: [39===sdram_a[7...0], sdram_a[15...8], sdram_b[15...8], sdram_b[7...0], sdram_c===0].
So, the last dqs group (sdram_a[7...0], or dq_pin[39...32]) could not be calibrated with all devices together. When I swap sdram_a[7...0] and sdram_a[15...8], I have only 3/5 (I attach reports for each variation of order, see the first line to define it).
Thanks!
