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Andrey_Fazan's avatar
Andrey_Fazan
Icon for New Contributor rankNew Contributor
4 years ago

calibration of ddr4 interface on 10AX066H4F34E3SG

Hello! I'm trying to implement DDR4 40bit-wide interface with 3 devices MT40A512M16LY-062E. When I connect only one of 3 devices to the project, calibration and data exchange do well, but when I conn...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Andrey,


Can you create a 32-bit data configuration and used the sdram_a[7...0] as the last group?


Thanks


Andrey_Fazan's avatar
Andrey_Fazan
Icon for New Contributor rankNew Contributor
4 years ago

Hi, Adzim

I created such interface. Both sdram_a[7...0] and sdram_a[15...8] can be calibrated with sdram_b and sdram_c. I also tried to create an interface with only sdram_a and sdram_b (without sdram_c). Calibration was not successful. I attach report for each situation (as always the order of connection is at the top of each document)