calibration of ddr4 interface on 10AX066H4F34E3SG

Hello sir,

I'm Adzim. Thanks for using Intel Community.

There are some possible causes that produce the calibration error.

But I need ask some questions first.

Have you tested all the 3 devices individually?

I mean connect one device to the project and tests it.

Repeat with another device.

Or the issue only happens when you trying to use 3 device all together?

Because of you are going to use multiple device, please check the following:

Do you enable the EMIF Debug Toolkit option?

Do you enable the address mirroring option?

There is a known issue when using the 10AX066 device.

You have to make sure that the reset is held for about 200ms after the initialization process.

Is that possible to know the calibration error?

Thanks,

Adzim

Hello, mr. Adzim!
I have tested each device individually (only one device was connected to the project). Calibration was successful in this case. This issue happens when I try to use 3 devices all together. And what about your checklist:
1. EMIF Debug Toolkit is enabled
2. How can I enable address mirroring option? (I use Quartus Prime Pro 20.2.0)
3. And how can I make reset to be held about 200ms after initialization?

And here is calibration status:

; Calibration Status Per Group ;
+-------+--------+----------------------+
; Group ; Status ; Error Stage ;
+-------+--------+----------------------+
; 0 ; Pass ; N/A ;
; 1 ; Pass ; N/A ;
; 2 ; Fail ; Read Per-bit Deskew ;
; 3 ; Fail ; Write Per-bit Deskew ;
; 4 ; Fail ; Write Per-bit Deskew ;

Hi Andrey_Fazan,

Thank you for sharing the calibration error.

Is the calibration always failed at that stage?

Which memory that the calibration is failing?

Can you try to disable the address and command leveling calibration?

You can set it in the IP Parameter Editor, under the Diagnostics tab,

select the Skip address/command leveling calibration.

I'm referring to the KDB in the link below. It's looks like the error is related.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/fb292783.html

The address mirroring option is in hidden parameter and I can see that the default value is already been enabled in Quartus Prime Pro 20.2.

Regards,

Adzim

Hi Andrey_Fazan,

Thanks for sharing the report.

Are you also able to attached the calibration report for the one device testing?

From the report, it's can be seen that the calibration is stopped at DQS2.

Can you identify which device that has been used for that group?

Can you check the connection on that device?

Can you confirm that all connections on your design are connected correctly?

Or if possible, can you test it on different board?

Thanks,

Adzim

Hi Andrey_Fazan,

Thanks for sharing the calibration reports.

I can see it as you mention it previously.

If that thus matter if you change the group for your device?

such as:-

- bank C - the first device (DQS0, DQS1)

- bank B - the second device (DQS2, DQS3)

- bank A - the third device (DQS4)

If it always stops the calibration at DQS2, it could be the process has been interrupted by the reset signal.

Can check that the reset signal is not triggered during the calibration process?

Regards,

Adzim

Hi, Adzim!

If that thus matter if you change the group for your device? - It is impossible to change group for devices because only 8 DQ pins from device "Bank C" are connected to the FPGA

Can check that the reset signal is not triggered during the calibration process? - Reset signal is not triggered

I attach also configuration list for EMIF example, hope, it can help to solve the problem

Thank you!

Hi Andrey_Fazan,

Thanks for sharing the EMIF IP configuration.

When I looked at your configurations, I can see that the ECC is not enable.

If I'm not mistaken, the 40bit = 32bit +8bit ECC.

Why not you disable the x8 SDRAM component and use both x16 SDRAM components to make a 32bit-wide interface?

Thanks,

Adzim

Hi Adzim,

Yes, our purpose is to use ddr4 40bit-wide interface with ECC, but ECC was disabled until successful calibration. Both enabling ECC and disabling x8 component didn't help, I attach these reports

Hi Andrey_Fazan,

Are you able to implement your design in different board?

Hi Andrey_Fazan,

Can you check the signal integrity of the board?

You can change the OCT value in the EMIF IP.

Can you also perform a simulation by changing the DQS group with other memory?

I mean here is like a memory A is connects to the Group 0 and 1.

Then connects it to the Group 2 and 3.

Regards,

Adzim