Forum Discussion

Andrey_Fazan's avatar
Andrey_Fazan
Icon for New Contributor rankNew Contributor
4 years ago

calibration of ddr4 interface on 10AX066H4F34E3SG

Hello! I'm trying to implement DDR4 40bit-wide interface with 3 devices MT40A512M16LY-062E. When I connect only one of 3 devices to the project, calibration and data exchange do well, but when I conn...
Andrey_Fazan's avatar
Andrey_Fazan
Icon for New Contributor rankNew Contributor
4 years ago

Hi, Adzim!

If that thus matter if you change the group for your device? - It is impossible to change group for devices because only 8 DQ pins from device "Bank C" are connected to the FPGA

Can check that the reset signal is not triggered during the calibration process? - Reset signal is not triggered

I attach also configuration list for EMIF example, hope, it can help to solve the problem

Thank you!