Burst write transaction on PCIe TX Interface on SOPC application

Is your component declaring that the burst width is at least 9 bits (since you are sending a burst of 256).

I haven't hooked up my bursting stuff to PCIe personally but others have and had good luck with it so it is possible to get good throughput.

Also I'm not sure what the PCIe max burst count is but I thought it was 128. If that's the case you are probably better off matching your master max burst count to 128 so that you can avoid any burst adapter logic that SOPC Builder will insert between your master and slave port. You'll get one regardless on the SDRAM side unless you decouple the burst counts on the read and write but that requires the read and write control logic to manage the bursts separately.

I would also recommend simulation or signaltapping the master and slave interface to see exactly what the traffic looks like to make sure it is actually the writes causing the throughput problem.

Dear BadOmen,

in my previous test there isn't any write on Tx Interface before burst, but I've done another test, attached in .stp with a no burst write operation before start burst.

As you can see in the .stp also during no burst write burst count of Tx Interface is always at 0x01 while burst count of Avalon MM Master is at 0x00.

Let me know your opinion.

Thank you.