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Altera_Forum
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16 years ago

Burst write transaction on PCIe TX Interface on SOPC application

Hi All, I've realized a Project with SOPC Builder including a PCIe IP, a DDR2 II controller and a custom SOPC components (with Master Avalon Interface inside) that manage a burst write from DDR2 I...
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Altera_Forum
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16 years ago

Actually I'm surprised the fabric didn't lock up when the master posted a burst write transaction of 0 beats (that is not allowed in Avalon-MM).