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Altera_Forum
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15 years ago

Burst write transaction on PCIe TX Interface on SOPC application

Hi All, I've realized a Project with SOPC Builder including a PCIe IP, a DDR2 II controller and a custom SOPC components (with Master Avalon Interface inside) that manage a burst write from DDR2 I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Dear BadOmen,

in my previous test there isn't any write on Tx Interface before burst, but I've done another test, attached in .stp with a no burst write operation before start burst.

As you can see in the .stp also during no burst write burst count of Tx Interface is always at 0x01 while burst count of Avalon MM Master is at 0x00.

Let me know your opinion.

Thank you.