BRAM "Read old data while writing" option for Cyclone V

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As I read in Embedded memory user guide, "Read old data during write" is not supported in M10K and M20K blocks. Since Cyclone V device has only M10K blocks, can I assume that "Read old data during write" is not possible in Cyclone V? If yes, what is the alternate solution for this? Looking forward for help.. Thanks.

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From what I read it is allowed in cyclone V for certain memory types (single clock or dual...). If in your case it is not allowed then check that you do really mean to read old data & write.

If that is required by your design then you could change your plan and read just before write by delaying write on same address.

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Thanks for reply.. I need true dual port BRAM with "Read old data while write" option. Read before write by delaying write could have been best option, but since I am migrating from older device to cyclone V, It was already designed to use this option. And modifying the design at this point of time is not feasible. Hence wanted to know if there is any alternate solution for this

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One option is using logic to implement ram(if small).

The other option I can think of is use rising edge to read and falling edge to write so that read is always before write (if timing helps).

Yu may also check in sim if wr/rd do occur together this could be hard t cover)

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One option is using logic to implement ram(if small).

The other option I can think of is use rising edge to read and falling edge to write so that read is always before write (if timing helps).

Yu may also check in sim if wr/rd do occur together this could be hard t cover)

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Thanks for your valuable suggestions kaz. What could be the reason for not supporting this feature in M10K block when it was available in earlier M9K block?

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Thanks for your valuable suggestions kaz. What could be the reason for not supporting this feature in M10K block when it was available in earlier M9K block?

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I think it is to do with silicon level and clocking scheme used around the ram. The actual answer is with Altera and I can only guess.

Normally - just like a register - one expects a read to read Q before it is updated by D but internally rams do not use clock per each cell (or do not use clock at all except on input/output registers)...