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Altera_Forum
Honored Contributor
Honored ContributorBRAM "Read old data while writing" option for Cyclone V
Hi, I am using Cyclone V device and I wanted to migrate one of the design which was targeted for xilinx device to Altera Cyclone V. And I want to use True Dual Port BRAM with "Read Old data while...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Thanks for your valuable suggestions kaz. What could be the reason for not supporting this feature in M10K block when it was available in earlier M9K block? --- Quote End --- I think it is to do with silicon level and clocking scheme used around the ram. The actual answer is with Altera and I can only guess. Normally - just like a register - one expects a read to read Q before it is updated by D but internally rams do not use clock per each cell (or do not use clock at all except on input/output registers)...
