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Altera_Forum
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8 years ago

BRAM "Read old data while writing" option for Cyclone V

Hi, I am using Cyclone V device and I wanted to migrate one of the design which was targeted for xilinx device to Altera Cyclone V. And I want to use True Dual Port BRAM with "Read Old data while...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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One option is using logic to implement ram(if small).

The other option I can think of is use rising edge to read and falling edge to write so that read is always before write (if timing helps).

Yu may also check in sim if wr/rd do occur together this could be hard t cover)

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Thanks for your valuable suggestions kaz. What could be the reason for not supporting this feature in M10K block when it was available in earlier M9K block?