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Thanks for reply.. I need true dual port BRAM with "Read old data while write" option. Read before write by delaying write could have been best option, but since I am migrating from older device to cyclone V, It was already designed to use this option. And modifying the design at this point of time is not feasible. Hence wanted to know if there is any alternate solution for this
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One option is using logic to implement ram(if small).
The other option I can think of is use rising edge to read and falling edge to write so that read is always before write (if timing helps).
Yu may also check in sim if wr/rd do occur together this could be hard t cover)
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