MUrba10
New Contributor
5 years agoBit slip port in E-TILE transceivers. Native PHY mode
Hello,
I have a question regarding bit slip functionality in Stratix 10 E-TILE transceivers, functioning in Native PHY mode. Other Intel FPGA transceivers have a dedicated bit slip port (for example rx_pma_clkslip in Stratix 10 H-Tile transceivers), which allows to instruct deserializer to skip one serial bit to achieve word alignment.
I wasn't able to find similar input in Stratix 10 E-TILE transceivers. How do I achieve similar functionality using E-TILE transceivers? Should I use PMA attribute "Rx Phase Slip" (0x000E)?
Thank you!