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MUrba10's avatar
MUrba10
Icon for New Contributor rankNew Contributor
5 years ago

Bit slip port in E-TILE transceivers. Native PHY mode

Hello, I have a question regarding bit slip functionality in Stratix 10 E-TILE transceivers, functioning in Native PHY mode. Other Intel FPGA transceivers have a dedicated bit slip port (for example...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

If you refer to the "Reconfiguring the Duplex PMA Using the Reset Controller in Automatic Mode" section in the E-Tile user guide, you would see RX phase slip is one of the step required. It is used to perform phase offset for the RX recovered clock to suit the new data rate.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin