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Altera_Forum
Honored Contributor
Honored ContributorAVALON_MM interface of TSE
Hello guys,
In my system ,I want to use TSE without Niosii.I have use it within NiosII and it works very well.I read or wrote the AVALON_MM interface in TSE module to config the inner registers,but it failed when I simulated with my own configuration modle. My question is wether the AVALON_MM can be read or write without NiosII.:confused: Thanks.31 Replies
Altera_ForumYes it can, you can drive the signals yourself. Be sure to use the waitrequest signal as specified in the Avalon specification.
- Altera_Forum--- Quote Start --- Yes it can, you can drive the signals yourself. Be sure to use the waitrequest signal as specified in the Avalon specification. --- Quote End --- daixiwen, First,thank you for your reply. I have write my own configuration module to config the registers.When I simulate the module with TSE,I see the waitrequest signal is always high.Due to this,I can't read or write any register.According to your opinion,what's the proplem. I appreciate your help!!;)
- Altera_Forum
the name of the signal explains this.
waitrequest .... request to wait ! if this is set to 1 then a master must obey this and wait until it is released. a master starts the transfer and sets the signals and a slave can assert waitrequest if the slave is not able to finish the transfer with this clock cycle. if the slave ha done his job (after ??? cycles) then he releases waitrequest to signal the master the transfer is finished. so as long as waitrequest is set to 1 a slave is not ready and data is not valid or computed. but it should go to 0 or it would be an infinite wait. as master who receives a wait is stalled. - Altera_Forum
First, be sure that you run the simulation for an enough long time. The component may need lots of cycles to initialize.
Second, check that you provide all the required clocks, for the Avalon MM interface, but also for the Avalon Streams. You may even need to provide an MII transmit clock. There is probably lots of clock domain crossing logic in the TSE, and failure on one clock could lock the component. - Altera_Forum
Thanks,michael.I know the meaning of waitrequest for master .What I don't understand is why it is always high in whole simulation process.Whatever,thank you for your reply!!!:D
daixiwen,I run simulation for 10us.Is it not enough long? Besides,I have give all clock signal to other interface.However,I will check it again,thank you~~:) - Altera_Forum
Is your reset or clock stuck?
Jake - Altera_Forum--- Quote Start --- Is your reset or clock stuck? Jake --- Quote End --- I set right value of clock and reset.I made mdc output and found it was right.But waitrequest was always 1. Is there other proplem may cause the unnormal phenomenon? Thanks,Jake.:) P.S.:the attachment is my project,could you help me to check it?
- Altera_Forum
Be careful that the reset signal on the MAC is active high, not low.
Altera provides an independent test bench for the TSE mac (see chapter 5 of the documentation). Can you run it and check the differences in the signals with your test bench? - Altera_Forum--- Quote Start --- Be careful that the reset signal on the MAC is active high, not low. Altera provides an independent test bench for the TSE mac (see chapter 5 of the documentation). Can you run it and check the differences in the signals with your test bench? --- Quote End --- How to run the test bench?Is modelsim used?:confused:
- Altera_Forum
Isn't it generated by the megawizard?
And yes, it probably needs to be run in Modelsim.
