arria10 PCIE IP Example design simulation error

Generate Example design with Arria 10 PCIE IP, modelsim simulation of the generated Example design, according to the steps: do msim_setup.tcl->ld_debug, ld_debug when the following error occurs:

Vlog-reportprogress 300-sv../../../ IP/pcie_example_design_tb pcie_example_design_inst_board_pins_bfm_ip altera_conduit_bfm_181 / sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq sv - LAltera_common_sv_packages - work altera_conduit_bfm_181

** Error: (vlog-7) Failed to open design unit file "../../../ IP/pcie_example_design_tb pcie_example_design_inst_board_pins_bfm_ip altera_conduit_bfm_181 / sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq sv "in read mode.

# No such file or directory. (errno = ENOENT)

In addition, the file /pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv was not found in the generated file and Quartus installation directory, please help ， thanks

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