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New Contributorarria10 PCIE IP Example design simulation error
Generate Example design with Arria 10 PCIE IP, modelsim simulation of the generated Example design, according to the steps: do msim_setup.tcl->ld_debug, ld_debug when the following error occurs:
Vlog-reportprogress 300-sv../../../ IP/pcie_example_design_tb pcie_example_design_inst_board_pins_bfm_ip altera_conduit_bfm_181 / sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq sv - LAltera_common_sv_packages - work altera_conduit_bfm_181
** Error: (vlog-7) Failed to open design unit file "../../../ IP/pcie_example_design_tb pcie_example_design_inst_board_pins_bfm_ip altera_conduit_bfm_181 / sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq sv "in read mode.
# No such file or directory. (errno = ENOENT)
In addition, the file /pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv was not found in the generated file and Quartus installation directory, please help ， thanks
5 Replies
SengKok_L_IntelRegular Contributor
Hi,
What is your PCIe IP setting (e.g. Gen2 or Gen3)?
Did you refer to the following link to generate the example design, and then go to the right directory to run the simulation?
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-a10-pcie-avst.pdf
Regards -SK
RLi1Quartus is 18.1 and Modelsim is starter edition 10.6d
- SengKok_L_Intel
It will be good if you can let us know if you are running at Gen2 or Gen 3? Besides, did you follow the above example design to run the simulation?
Regards -SK
- RLi1
- PCIE Gen2 x8. Yes ， I follow the link to generate the example design, Follow the steps above to emulate the example design. The same error still occurs
- SengKok_L_Intel
Hi Richard, There is a problem to run PCIe Gen2 simulation, and this is fixed in v19.4. I would suggest you use the latest Quartus version if possible.
Regards -SK
