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RLi1's avatar
RLi1
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5 years ago

arria10 PCIE IP Example design simulation error

Generate Example design with Arria 10 PCIE IP, modelsim simulation of the generated Example design, according to the steps: do msim_setup.tcl->ld_debug, ld_debug when the following error occurs:

Vlog-reportprogress 300-sv../../../ IP/pcie_example_design_tb pcie_example_design_inst_board_pins_bfm_ip altera_conduit_bfm_181 / sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq sv - LAltera_common_sv_packages - work altera_conduit_bfm_181

** Error: (vlog-7) Failed to open design unit file "../../../ IP/pcie_example_design_tb pcie_example_design_inst_board_pins_bfm_ip altera_conduit_bfm_181 / sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq sv "in read mode.

# No such file or directory. (errno = ENOENT)

In addition, the file /pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv was not found in the generated file and Quartus installation directory, please help ， thanks

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5 Replies

  • RLi1's avatar
    RLi1
    Icon for New Contributor rankNew Contributor
    5 years ago

    Quartus is 18.1 and Modelsim is starter edition 10.6d

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    It will be good if you can let us know if you are running at Gen2 or Gen 3? Besides, did you follow the above example design to run the simulation?

    Regards -SK

  • RLi1's avatar
    RLi1
    Icon for New Contributor rankNew Contributor
    5 years ago
    • PCIE Gen2 x8. Yes ， I follow the link to generate the example design, Follow the steps above to emulate the example design. The same error still occurs

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  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi Richard, There is a problem to run PCIe Gen2 simulation, and this is fixed in v19.4. I would suggest you use the latest Quartus version if possible.

    Regards -SK