Forum Discussion
RLi1
New Contributor
6 years agoarria10 PCIE IP Example design simulation error
Generate Example design with Arria 10 PCIE IP, modelsim simulation of the generated Example design, according to the steps: do msim_setup.tcl->ld_debug, ld_debug when the following error occurs: Vlo...
SengKok_L_Intel
Regular Contributor
6 years agoHi Richard, There is a problem to run PCIe Gen2 simulation, and this is fixed in v19.4. I would suggest you use the latest Quartus version if possible.
Regards -SK