Forum Discussion

RLi1's avatar
RLi1
Icon for New Contributor rankNew Contributor
6 years ago

arria10 PCIE IP Example design simulation error

Generate Example design with Arria 10 PCIE IP, modelsim simulation of the generated Example design, according to the steps: do msim_setup.tcl->ld_debug, ld_debug when the following error occurs: Vlo...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

It will be good if you can let us know if you are running at Gen2 or Gen 3? Besides, did you follow the above example design to run the simulation?

Regards -SK