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Honored ContributorArria II GX Devkit TSE RGMII Help
Hi all,
I've been struggling to get the ethernet port working on the Arria II devkit (after getting flash, DDR2, and DDR3 working). I am mimicking the code found in bts_config, but using vhdl, qsys, and quartus 11.0sp1. Just aiming to get the simple socket server running. The pre-loaded webserver works on power-up, so the HW is good. Here is the startup output Simple Socket on my fpga:
INFO : TSE MAC 0 found at address 0x00001400
INFO : PHY Marvell 88E1111 found at PHY address 0x00 of MAC Group
INFO : PHY - Automatically mapped to tse_mac_device
INFO : PHY - Restart Auto-Negotiation, checking PHY link...
INFO : PHY - Auto-Negotiation PASSED
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO : PHY - Checking link...
INFO : PHY - Link not yet established, restart auto-negotiation...
INFO : PHY - Restart Auto-Negotiation, checking PHY link...
INFO : PHY - Auto-Negotiation PASSED
INFO : PHY - Link established
INFO : PHY - Speed = 100, Duplex = Full
OK, x=0, CMD_CONFIG=0x00000000
MAC post-initialization: CMD_CONFIG=0x04000203
RX descriptor chain desc (1 depth) created
mctest init called
IP address of et1 : 0.0.0.0
DHCP timed out, going back to default IP address(es)- The PHY expects clock to be skewed, but this can be fixed by writing to a PHY reg with MDIO. It appears "Enable RGMII Timing Control" is doing that.
- Simple socket must be modified for RGMII.
- RGMII does not support 10/100 speeds.
13 Replies
Altera_ForumTry to use static IP address and test if ethernet works at all.
- Altera_Forum--- Quote Start --- Try to use static IP address and test if ethernet works at all. --- Quote End --- Sorry, forgot to mention I already tried that.
- Altera_Forum
did You add driver control for RGMII in Your system?
Create .c file in Your project and add this:
This is added in Simple Socket Server RGMII example. If still not work, check if You can ping Your board? If not, check timing issues. RGMII bus on gigabit speed is hard to meet timing./* REQUIRED ONLY IF NETWORK IS RGMII */ # ifdef ALT_INICHE # include "ipport.h"# endif # include "system.h"# include "altera_avalon_tse.h"# include "altera_avalon_tse_system_info.h" alt_tse_system_info tse_mac_device = { TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(TSE_MAC, 0, SGDMA_TX, SGDMA_RX, TSE_PHY_AUTO_ADDRESS, &marvell_cfg_rgmii, DESCRIPTOR_MEMORY) }; - Altera_Forum
TO_BE_DONE
- Altera_Forum
The example project should run fine. I use RGMII bus on my Cyclone III board and it works fine either 10/100 or 1000Mbps.
- Altera_Forum--- Quote Start --- The example project should run fine. I use RGMII bus on my Cyclone III board and it works fine either 10/100 or 1000Mbps. --- Quote End --- That's good to hear. That means I must have done something wrong in the FPGA code. I guess it is time to break out signaltap. Thanks
- Altera_Forum--- Quote Start --- That's good to hear. That means I must have done something wrong in the FPGA code. I guess it is time to break out signaltap. Thanks --- Quote End --- Well, I'm having the SAME issues... Although, sometimes the PHY does not return from reset. Does this tell us anything? Mike
- Altera_Forum
If it's Marvell 88E1111, then check the datasheet. You need to keep it in reset for some time. I've made 16bit counter that runs out in about 0.5sec and then releases the reset.
You can check if this is the same issue: wire phy reset signal to the button, which resets all the system. Run the system, push reset button and upload Nios once more. Now ethernet should work. - Altera_Forum
Did you guys ever get it working? If so, what did you do? I am having the same problem.
- Altera_Forum--- Quote Start --- Did you guys ever get it working? If so, what did you do? I am having the same problem. --- Quote End --- Not sure what the "same problem" is, but I did finally get ethernet working. AN 647 was helpful. It contains a qsys example for the Arria II GX 125 devkit. The 125 and 260 are pin compatible, so I just changed the fpga type in the .qsf file and was able to synthesize a working system. From that I derived my own top-level from scratch using device settings found in the example project. I don't have DDR2 working at the moment (but did in the past), but have not put much effort into it since DDR3 works and is all I need for now.
