Arria 10 Transceiver Native PHY for simply connection.. problems!

Good 2018 to everyone!

I'm attempting to simulate (Quartus Prime 17.0.2+Altera Modelsim) a simply Transceiver application: TX/RX single lane at 5,250 Gbps link between arria10 boards

I'm started from A10_SIBoard_SuperliteII_Video_1_Lane_10Gbps demo example project , changing some parameters to adapt application to my rate

I use Basic (enhanced PCS) mode, 64/66 (2 controls bit) , data rate 5250 Mhz. Internal Scrambler could be set or not.. my change is resumed here:

parameter

superliteii_video_1lane_10gbps

my project

XTAL *

148.5 Mhz

125 Mhz -> ½ divider

ATX PLL in

148.5 Mhz

62.5 Mhz

ATX PLL out -> tx_serial_clk0

5197.5 Mhz

2625 Mhz

Serial line rate

10.395 Gbps

5.25 Gbps

Tx parallel words rate

157.5 Mhz

65.625 Mhz

Rx parallel words rate

157.5 Mhz

65.625 Mhz

Cdr_ref_clock (Clock & data recovery transceiver)

148.5 Mhz

62.5 Mhz

RX CDR reference clock frequency

148.5 Mhz

62.5 Mhz

RX PMA & RX PMA dividers

33

40

Then, I Try to simulate a simply loop (internal loop Serialpbken)

I have a bad behaviour:

1) the native IP resets seems too short: I program 70000 ns but IP resets give me very short times

2) the phy runs, it create the rx clocks well.. but the received words (simply 64 bit counter sequence for test) lost one word every 10 / 20... !!! I tried with and without scrambler, I fix control bits to 01 but

the phy works bad..... Have you similar experiences with this object???

Thank you to everyone for any suggestion

Phil