Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Arria 10 Transceiver Native PHY for simply connection.. problems!

Good 2018 to everyone! I'm attempting to simulate (Quartus Prime 17.0.2+Altera Modelsim) a simply Transceiver application: TX/RX single lane at 5,250 Gbps link between arria10 boards I'm s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi Phil,

I have a problem very similar to yours.

Can i ask you an information? What is the requirement for clock limit violation?

Have you connect tx/rx clock out into TX/rx core clock in? The pma divider is for coreclock in?

Thanks,

Marco