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Altera_Forum
Honored Contributor
8 years agoArria 10 Transceiver Native PHY for simply connection.. problems!
Good 2018 to everyone! I'm attempting to simulate (Quartus Prime 17.0.2+Altera Modelsim) a simply Transceiver application: TX/RX single lane at 5,250 Gbps link between arria10 boards I'm s...
Altera_Forum
Honored Contributor
8 years agoChecking transceiver parallelel data out: phy seems cut one sample every 9/10 .. after some time, the output restart rewriting old samples..
but the recovered rx clock is correct: rx_is_locked_data signal is always high, cal_busy is always low! All check signals are correct... I cannot understand what is the problem! I understand that the 2 control bits are sent/received in trasparent mode, and I would use them to sync may frame... but at this stage I fixed them to test the phy! It fails!