Forum Discussion
Altera_Forum
Honored Contributor
8 years agoChecking transceiver parallelel data out: phy seems cut one sample every 9/10 .. after some time, the output restart rewriting old samples..
but the recovered rx clock is correct: rx_is_locked_data signal is always high, cal_busy is always low! All check signals are correct... I cannot understand what is the problem! I understand that the 2 control bits are sent/received in trasparent mode, and I would use them to sync may frame... but at this stage I fixed them to test the phy! It fails!