API calls failed while running PCIe DMA transfer example design

Hi Wincent,

I am very sorry for a bit delay in response. I was in a short vacation, and did not have internet access much of the time.

As I was working in this project from last March, and was in a communication with an intel employee. He tried to help me in debugging and he was kind enough to have a couple of meeting with me to fix the issue. But he told me that the issue looks out of his expertise and he believed that the issue is somewhat related to the PCIe DMA part of the modified design (I mean adding the counter FIFO somehow alters the the DMA transfer example design), But he could not pin-point this. He suggested me to open a new thread with PCIe tag. So I would really appreciate if you could give me directions to solve this issue.

I have a couple of questions regarding your suggestions,

1. "Verify the connection and configuration: Ensure that the connections between your custom IP, Avalon FIFO IP, PCIe DMA IP, and DDR4 memory are correctly established and properly configured. Check the signal interfaces, clock domains, data widths, and address mappings to ensure consistency and correctness."

As I am comparatively new to Quartus Prime Pro, I would like to have bit more details regarding this. I wonder is there any specific place to cross-check all at a place like compilation report (message)? . Or have to check them starting from the stage where we add them in the Platform Designer System.

2. "Debugging the API call failure".

I would like to know that I have simulated the counter+FIFO stage and simulation looks fine (I have used modelsim free version for that) But unfortunately I did not find a way to simulate the whole design (counter + FIFO + PCIe DMA transfer example). As the modified PCIe DMA transfer example design has Avalon bus and its inherent complexity, I found its not as simple as simulating a combination of IP's by executing the simulation script (https://www.youtube.com/watch?v=eviC0jP90ZA&t=11s). Here my main issue was get the top level simulation test bench file for the whole design and I was confused how to do it for the PCIe IP?. Do you have any suggestion for doing the simulation of the whole design?

Debug print statements you mean in the API script?

3. "Verify the correctness of the DMA read process"

Any suggestion from your side to do this?

4. "Analyze error codes and messages" :

For sure its in my immediate todo list and I will update you the result soon. But I am very sorry to say I found Terasic document is not that helpful for the beginners like me and it does not have much information in it.

Thank you very much and looking forward to hearing from you.