Hi Sijith,
To be honest, I does not try this before.
I check the track record, I does not see any same implementation before as well.
However I can lay down some of the suggestion for you to proceed further.
- Verify the connection and configuration: Ensure that the connections between your custom IP, Avalon FIFO IP, PCIe DMA IP, and DDR4 memory are correctly established and properly configured. Check the signal interfaces, clock domains, data widths, and address mappings to ensure consistency and correctness.
- Debugging the API call failure: If the API call is failing to retrieve the expected data from the FIFO, it's essential to debug the issue step by step. You can add debug print statements or utilize simulation tools to trace the flow of data from the Avalon FIFO IP to the PCIe DMA IP and then to the host PC. Monitor the status and signals at each stage to identify any potential issues, such as incorrect pointer assignments, data alignment problems, or synchronization issues between different clock domains.
- Verify the correctness of the DMA read process: Make sure that the DMA read process, specifically the part you retained from the example code, is correctly configured and operates as expected. Check the pointer assignments, buffer sizes, and any required memory mappings to ensure that the DMA read process can access the correct data from the DDR4 memory.
- Analyze error codes and messages: If the API call is returning an error code or generating error messages, analyze them to understand the specific issue or failure reason. Cross-reference the error codes with the documentation provided by the Terasic example design to gain insights into the potential causes of the problem.
Hope this can help you.
Regards,
Wincent_Intel
Occasional Contributor
