Occasional Contributor
Regular ContributorHi,
Theoretically, DMA function is not work for FIFOs but it is only work for memory that have physical address. FIFO unlike a memory (DDR3) and no address associate with it. Thus, for FIFO, we usually used write/read32.
Regards,
Wincent_Intel
Occasional ContributorHi,
Sorry If my question was not clear. Actually, I my project is to stream data generated in a custom IP (a counter here) to a FIFO (Avalon FIFO IP) using an Avalon streaming interface. Then this data in FIFO should go into the DDR4 memory. The data thus written at the DDR4 should undergo DMA transfer to the host PC through PCIe.
For this, I was using the default PCIe DMA transfer example design (that given by the Terasic) and I have added the custom IP and Avalon FIFO IP with the PCIe DMA transfer example design (I can send the design files if you would like to see how they are connected in Platform Designer System).
In the API code (API in the PCIe_DDR4.cpp provided by the Terasic, I did comment out the data generation part and the DMA write portion. I just retained the DMA read portion and trying to print the *pRead values (Please see the lines 246 of the PCIe_DDR4.cpp files attached) that is supposed to fill by the data from the FIFO. Also attaching the verilog counter code used for the custom IP generation.
Just curious that any reason for the API call failure (that evident from my explanation)?, If so please give recommendation/suggestion to go forward?
Please let me know if you have any question.
