altsyncram simulation - X output?

Hi,

I'm trying to simulate a dual-port block ram using altsyncram, but the output(q_a, q_b) of the block ram is X when initialized. According to manual it should be set to zero. I don't understand why this is happening - any suggestion will be appreciated.

Following is the way I instantiate it:

library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity mem_2p_m9k is
    generic(
        addr_width : integer := 12;
        num_words : integer := 4096;
        data_width : integer := 16
    );
    port(
        clk : in std_logic;
        addr_a : in std_logic_vector(addr_width-1 downto 0);
        addr_b : in std_logic_vector(addr_width-1 downto 0);
        datain_a : in std_logic_vector(data_width-1 downto 0);
        datain_b : in std_logic_vector(data_width-1 downto 0);
        wren_a : in std_logic;
        wren_b : in std_logic;
        q_a : out std_logic_vector(data_width-1 downto 0);
        q_b : out std_logic_vector(data_width-1 downto 0)
    );
end mem_2p_m9k;
architecture arch of mem_2p_m9k is
    component altsyncram
    GENERIC (
        address_reg_b        : STRING;
        clock_enable_input_a        : STRING;
        clock_enable_input_b        : STRING;
        clock_enable_output_a        : STRING;
        clock_enable_output_b        : STRING;
        indata_reg_b        : STRING;
        intended_device_family        : STRING;
        lpm_type        : STRING;
        numwords_a        : NATURAL;
        numwords_b        : NATURAL;
        operation_mode        : STRING;
        outdata_aclr_a        : STRING;
        outdata_aclr_b        : STRING;
        outdata_reg_a        : STRING;
        outdata_reg_b        : STRING;
        power_up_uninitialized        : STRING;
        ram_block_type        : STRING;
        read_during_write_mode_mixed_ports        : STRING;
        read_during_write_mode_port_a        : STRING;
        read_during_write_mode_port_b        : STRING;
        widthad_a        : NATURAL;
        widthad_b        : NATURAL;
        width_a        : NATURAL;
        width_b        : NATURAL;
        width_byteena_a        : NATURAL;
        width_byteena_b        : NATURAL;
        wrcontrol_wraddress_reg_b        : STRING
    );
    PORT (
            wren_a    : IN STD_LOGIC ;
            clock0    : IN STD_LOGIC ;
            wren_b    : IN STD_LOGIC ;
            address_a    : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
            address_b    : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
            q_a    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
            q_b    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
            data_a    : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
            data_b    : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
    );
    END COMPONENT;
    
    begin
    mem_inst: altsyncram
    generic map(
        address_reg_b => "CLOCK0",
        clock_enable_input_a => "BYPASS",
        clock_enable_input_b => "BYPASS",
        clock_enable_output_a => "BYPASS",
        clock_enable_output_b => "BYPASS",
        indata_reg_b => "CLOCK0",
        intended_device_family => "Stratix III",
        lpm_type => "altsyncram",
        numwords_a => num_words,
        numwords_b => num_words,
        operation_mode => "BIDIR_DUAL_PORT",
        outdata_aclr_a => "NONE",
        outdata_aclr_b => "NONE",
        outdata_reg_a => "NONE",
        outdata_reg_b => "NONE",
        power_up_uninitialized => "FALSE",
        ram_block_type => "M9K",
        read_during_write_mode_mixed_ports => "DONT_CARE",
        read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
        read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
        widthad_a => addr_width,
        widthad_b => addr_width,
        width_a => data_width,
        width_b => data_width,
        width_byteena_a => 1,
        width_byteena_b => 1,
        wrcontrol_wraddress_reg_b => "CLOCK0"
        )
    port map(
            wren_a => wren_a,
            clock0 => clk,
            wren_b => wren_b,
            address_a => addr_a,
            address_b => addr_b,
            q_a    => q_a,
            q_b    => q_b,
            data_a => datain_a,
            data_b => datain_b
        );
end arch;