ALTPLL 600MHz output

Question

Hi,

I need to get clarification on the ALTPLL in the Megawizard.

I'm using a DE3 board and I want to run my verilog-code in 600MHz (just some simple registers for now), this should be possible as far as i have read. To achive this i want to use the PLL to generate a clock of 600MHz from the base 50MHz. But when creating this with the PLL, the output c0 clock signal is just a pure sine according to my oscilliscope and EXT_CLK output. This causes my verilog hardware to behave very weird and not output anything as expected.

When reducing the PLL output to 50MHz, i get a good looking c0 and everything works just fine.

Can't the PLL produce a proper output clock at 600MHz? How is this configured? Can't seem to get it to work after several hours! Some advice please :)

altera_forum · Answer

Unless your oscilloscope and probe bandwidth is 2 GHz or better above, you won't see anything but a sine. Of course you need a suitable differential I/O standard with correct termination. If you don't have a multi GHz active probe, a direct connected 50 ohm cable can reproduce the waveform.

Weird behaviour of your "verilog hardware" is rather a problem of timing violations or other design errors. To make it understandable, you should briefly tell what you are trying to achieve and how you detect "weird behaviour".

P.S.: I see, that Stratix III can also achieve up to 1000 MHz toggle rate with some single ended IO standards. With the DE3 board, it's probably best to use the SMA clock output for this tests. The external output's waveform hasn't anything to do with waveforms of the internal clock tree, but frequency and jitter performance can be monitored.

altera_forum · Answer

My oscilloscope is a 2GSa / 300MHz, and it is connected (@ 50Ohm) with sma-connector at CLK_OUT. In the FPGA i have connected the altpll output to CLK_OUT and i was hoping to see a 600MHz clock output, but i only see a 600MHz sine wave at the oscilloscope.

I'm generating a PRBS with 7 registers, so simply shifting bits. The output bit is observerd in the oscilloscope and this is where i detect my errors;

The output pattern looks exacly as expected when running at ~50MHz with the PLL, but when the frequency goes higher is looks more or less like.. well nothing really, just a wierd looking waveform instead of strict bitpattern.

Is this really a problem with my measurement rather than the FPGA perhaps? I will use signaltap to look further into it right now.

altera_forum · Answer

Signaltap reveals that everything is working just fine, seems like i need a much faster oscilloscope then ;)

altera_forum · Answer

--- Quote Start ---  seems like i need a much faster oscilloscope then  --- Quote End ---   Yes, as said. I also wonder, at which DE-3 connector you accessed the PRBS output?

altera_forum · Answer

--- Quote Start ---  Yes, as said. I also wonder, at which DE-3 connector you accessed the PRBS output?  --- Quote End ---     GPIO0 with probe

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ALTPLL 600MHz output

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