My oscilloscope is a 2GSa / 300MHz, and it is connected (@ 50Ohm) with sma-connector at CLK_OUT. In the FPGA i have connected the altpll output to CLK_OUT and i was hoping to see a 600MHz clock output, but i only see a 600MHz sine wave at the oscilloscope.
I'm generating a PRBS with 7 registers, so simply shifting bits. The output bit is observerd in the oscilloscope and this is where i detect my errors;
The output pattern looks exacly as expected when running at ~50MHz with the PLL, but when the frequency goes higher is looks more or less like.. well nothing really, just a wierd looking waveform instead of strict bitpattern.
Is this really a problem with my measurement rather than the FPGA perhaps? I will use signaltap to look further into it right now.