Forum Discussion
Honored ContributorALTLVDS pins io standard
hi,
I am using ALTLVDS megacore for serialization and deserialization. the serializer has tx_out : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) and the deserializer has rx_in : IN STD_LOGIC_VECTOR (0 DOWNTO 0) when i assign the io standar for these pins as LVDS, the pin planner creates tx_out(0)n & rx_in(0)n. when i assign these pins to diffential pain then during fitter i get the below error Error: Found two LVDS low registers instead of one! is am i connecting pins correctly or do i have to add an alt_inbuff_diff & alt_outbuff_diff?11 Replies
Altera_ForumCan you post your current pin assignments either from your QSF or by exporting a TCL from the pin planner?
Jake- Altera_Forum
It's sufficient to assign LVDS IO standard to the logical pin. The location must be the positive pin of a differential pair. The negative pin is also displayed in the Pin Planner tool, but you don't need to assign it anyway. You can even delete the negative pin entry from the Pin Planner list. The handling of negative differential pins isn't actually consistent throughout the different Quartus tools, it seems confusing in part.
- Altera_Forum
pls. find the archived project attached, i tried the methods sugessted...but did not work
- Altera_Forum
quartus 9.1sp1 fitter error
Error: Found two LVDS low registers instead of one! Error: Found two LVDS high registers instead of one! for this piece of code generated by megawizad // synopsys translate_off initial dataout_h_reg = 0; // synopsys translate_on always @ ( posedge clock) dataout_h_reg <= ddio_h_reg; // synopsys translate_off initial dataout_l_latch = 0; // synopsys translate_on always @ ( negedge clock) dataout_l_latch <= ddio_l_reg; // synopsys translate_off initial dataout_l_reg = 0; // synopsys translate_on always @ ( posedge clock) dataout_l_reg <= dataout_l_latch; // synopsys translate_off initial ddio_h_reg = 0; // synopsys translate_on always @ ( posedge clock) ddio_h_reg <= datain; // synopsys translate_off initial ddio_l_reg = 0; // synopsys translate_on always @ ( negedge clock) ddio_l_reg <= datain; assign dataout_h = dataout_l_reg, dataout_l = dataout_h_reg; endmodule //RxLVDS_lvds_ddio_in - Altera_Forum
The problem is, that Quartus doesn't accept this port definitions (1-bit arrays):
Define the ports as std_logic, use additional wire signals and assign them to the Rx/Tx IP:RxData : in std_logic_vector(0 downto 0); -- IP data transmit TxData : out std_logic_vector(0 downto 0); -- IP data transmit
Then your code compiles without problems.signal RxData0 : std_logic_vector(0 downto 0); signal TxData0 : std_logic_vector(0 downto 0); ... TxData <= TxData0(0); RxData0(0) <= RxData; - Altera_Forum
I still get those fitter errors if i assign "LVDS" IO standard to RxData & TxData, i am making it sure that pin assignments are done correctly in pin planner
- Altera_Forum
No idea how you achieve it, as said, the design compiled correctly (with Quartus 9.0) after changing the top level to the version, I posted above. I'll send the complete design, too.
- Altera_Forum
Thank you very much...the project archive which u send is getting compiled.....just wondering why it did not compiled in quartus 9.1SP1
thanks again for the help - Altera_Forum
FvM,
one thing i have observed in ur project is that u have assigned pin locations to the internal signals i.e. Rx_Data[0] and Tx_Data[0], this is some thing i have learned new. - Altera_Forum
But I didn't assign them intentionally. They have been left from your design. I see now, that Quartus did not assign LVDS IO-standard for the renamed pins. If I assign it anew, the error reappears. In other words, my suggestion does not work.
It seems to me, that something is wrong with the newer alt_lvds MegaFunction, or with the way you invoked it. I'll try to recreate the respective module and see, if it can be connected to LVDS IO pins as I do since many years.
