ALTLVDS pins io standard

quartus 9.1sp1 fitter error

Error: Found two LVDS low registers instead of one!

Error: Found two LVDS high registers instead of one!

for this piece of code generated by megawizad

// synopsys translate_off

initial

dataout_h_reg = 0;

// synopsys translate_on

always @ ( posedge clock)

dataout_h_reg <= ddio_h_reg;

// synopsys translate_off

initial

dataout_l_latch = 0;

// synopsys translate_on

always @ ( negedge clock)

dataout_l_latch <= ddio_l_reg;

// synopsys translate_off

initial

dataout_l_reg = 0;

// synopsys translate_on

always @ ( posedge clock)

dataout_l_reg <= dataout_l_latch;

// synopsys translate_off

initial

ddio_h_reg = 0;

// synopsys translate_on

always @ ( posedge clock)

ddio_h_reg <= datain;

// synopsys translate_off

initial

ddio_l_reg = 0;

// synopsys translate_on

always @ ( negedge clock)

ddio_l_reg <= datain;

assign

dataout_h = dataout_l_reg,

dataout_l = dataout_h_reg;

endmodule //RxLVDS_lvds_ddio_in