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Altera_Forum
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16 years ago

ALTLVDS pins io standard

hi, I am using ALTLVDS megacore for serialization and deserialization. the serializer has tx_out : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) and the deserializer has rx_in : IN STD_LOGIC_VECTOR ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The problem is, that Quartus doesn't accept this port definitions (1-bit arrays): 

RxData : in std_logic_vector(0 downto 0);  -- IP data transmit
TxData : out std_logic_vector(0 downto 0);  -- IP data transmit

Define the ports as std_logic, use additional wire signals and assign them to the Rx/Tx IP: 

signal RxData0 : std_logic_vector(0 downto 0);
signal TxData0 : std_logic_vector(0 downto 0);
...
TxData <= TxData0(0);
RxData0(0) <= RxData;

Then your code compiles without problems.