Altera Simple Dual Port RAM -- Read cycle latency

Question

Hi all,

I use in my design a altsyncram, simple dual-port RAM, generated by MegaWizard. It is 4096 words deep, with 14-bit words input, with a single clock for both Port A and B.

When performing a basic read access operation, I observe a 2 clocks ticks latency. By that I mean, I assert my read_enable signal, with relevant address on the address bus, and data become available 2 clock ticks after read_enable assertion.

I want it to be one clock tick only. Is it possible with that type of memory?

FYI, when designing the core, under the 'Regs/Clkens', I unticked the 'Read Outputs q_a/q_b'.

thanks for your help on that!

altera_forum · Answer

Thanks,

the problem was in my wrapper for the altsyncram. Where the core is instantiated , I changed the "outdata_reg_a" to "UNREGISTERED" and now it works, there's only one clock cycle latency before data output is valid.

Thanks again, problem solved!

altera_forum · Answer

If read_enable is synchronous with the clock, when it's asserted (1st ), its registering is made at next clock (2nd) cycle.

jiayi_h_intel · Answer

Thanks. This answer solved the same problem in my design.

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Altera Simple Dual Port RAM -- Read cycle latency

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