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Altera_Forum
Honored Contributor
Honored ContributorAltera Simple Dual Port RAM -- Read cycle latency
Hi all, I use in my design a altsyncram, simple dual-port RAM, generated by MegaWizard. It is 4096 words deep, with 14-bit words input, with a single clock for both Port A and B. When pe...
Altera_ForumHonored Contributor
Honored ContributorThanks,
the problem was in my wrapper for the altsyncram. Where the core is instantiated , I changed the "outdata_reg_a" to "UNREGISTERED" and now it works, there's only one clock cycle latency before data output is valid. Thanks again, problem solved!
Jiayi_H_Intel
Occasional Contributor
Occasional ContributorThanks. This answer solved the same problem in my design.
