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Altera_Forum
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16 years ago

Altera Simple Dual Port RAM -- Read cycle latency

Hi all, I use in my design a altsyncram, simple dual-port RAM, generated by MegaWizard. It is 4096 words deep, with 14-bit words input, with a single clock for both Port A and B. When pe...
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Altera_Forum
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16 years ago

If read_enable is synchronous with the clock, when it's asserted (1st ), its registering is made at next clock (2nd) cycle.