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IOzan's avatar
IOzan
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Altera PLL is not working

Hi,

I'm trying to implement the Altera PLL from the IP catalog and no matter what I do- this simple cure is not working! (outclk_0 is constantly red signal in ModelSim). I'm working with Quartus Prime Lite Edition 17.1, ModelSim 10.5b and 5CEFA7F31I7 Cyclone V FPGA (EVM).

My ref clock is 50MHz and the desired and the actual is 48MHz. The other parameters are default (Direct, Integer-N PLL, Phase shift 0ps, D.C=50%, with locked output signal and input reset signal (active high but I even tried to toggle is in 1Hz).

What could possibly be the cause for the standard PLL cure???

Help…

Idan

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6 Replies

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi Idan,

    1. Have you applied reset?

    Try applying reset and given appropriate inputs to get the expected output.

    Regards

    Anand

    • IOzan's avatar
      IOzan
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi,

      I did… as I mentioned, I even toggle the reset at 1Hz. The ref clk is always present at the input signal.

      What else can I do to operate the PLL cure?

      Help…

      Idan

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi Idan,

    Are you using just PLL IP stand-alone or initiating PLL IP on top-level HDL for simulation? Check the connectivity of the ports or pins.

    Try after deleting the work folder from the simulation directory.

    Attached some images.

    Regards

    Anand