Forum Discussion

IOzan's avatar
IOzan
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Altera PLL is not working

Hi, I'm trying to implement the Altera PLL from the IP catalog and no matter what I do- this simple cure is not working! (outclk_0 is constantly red signal in ModelSim). I'm working with Quart...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Idan,

Are you using just PLL IP stand-alone or initiating PLL IP on top-level HDL for simulation? Check the connectivity of the ports or pins.

Try after deleting the work folder from the simulation directory.

Attached some images.

Regards

Anand

    • IOzan's avatar
      IOzan
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      And the complete code that is not working (PLL output is all red (U)).

      What can I do to make it work?

      Can you try to run the code in your Quartus and ModelSim versions?

      Thanks,

      Idan

    • AnandRaj_S_Intel's avatar
      AnandRaj_S_Intel
      Icon for Regular Contributor rankRegular Contributor
      6 years ago

      Hi Idan,

      Your design looks good, You have to recheck the simulation steps. Please read msim_setup.tcl(Simple_counter_PLLC\Filter_PLL_C_sim\mentor) file which will help in simulation step if you have top level file.

      I have attached the modelsim transcript and image. save below code as mentor.do and run

      set QSYS_SIMDIR C:/<Directory>/Simple_counter_PLLC/Filter_PLL_C_sim
source $QSYS_SIMDIR/mentor/msim_setup.tcl
 
dev_com
set TOP_LEVEL_NAME tb_Simple_counter
elab

      Regards

      Anand